Samsung S3C2451X User Manual page 497

S3C2451X RISC MICROPROCESSOR
PRESENT STATE REGISTER
This register contains the SD Command Argument.
Register
PRNSTS0
PRNSTS1
Name Bit
[31:25] Reserved
CMD Line Signal Level (RO)
PRNT [24]
This status is used to check the CMD line level to recover from errors, and for
CMD
debugging.
Note : CMD port is mapped to SD0_CMD pin
[23:20] DAT[3:0] Line Signal Level (RO)
PRNT
This status is used to check the DAT line level to recover from errors, and for
DAT
debugging. This is especially useful in detecting the busy signal level from DAT[0].
D23 : DAT[3]
D22 : DAT[2]
D21 : DAT[1]
D20 : DAT[0]
Note : DAT port is mapped to SD0_DAT pin
Write Protect Switch Pin Level (RO)
PRNT [19]
The Write Protect Switch is supported for memory and combo cards.
WP
This bit reflects the SDWP# pin.
1 = Write enabled (SDWP#=1)
0 = Write protected (SDWP#=0)
Note : SDWP# port is mapped to SD0_nWP pin, In S3C2451 case, SD#_nWP port
is fixed to High.
Card Detect Pin Level (RO)
PRNT [18]
This bit reflects the inverse value of the SDCD# pin. Debouncing is not performed on
CD
this bit. This bit may be valid when Card State Stable is set to 1, but it is not
guaranteed because of propagation delay. Use of this bit is limited to testing since it
must be debounced by software.
1 = Card present (SDCD#=0)
0 = No card present (SDCD#=1)
Note : SDCD# port is mapped to SD0_nCD pin, In S3C2451 case,
SD2_nCD(Channel 2) port is fixed to LOW.
Card State Stable (RO)
STBL [17]
This bit is used for testing. If it is 0, the Card Detect Pin Level is not stable. If this bit
CARD
is set to 1, it means the Card Detect Pin Level is stable. No Card state can be
detected by this bit is set to 1 and Card Inserted is set to 0. The Software Reset
For All in the Software Reset register shall not affect this bit.
1 = No Card or Inserted
0 = Reset or Debouncing
Card Inserted (RO)
INSCA [16]
This bit indicates whether a card has been inserted. The Host Controller shall
RD
debounce this signal so that the Host Driver will not need to wait for it to stabilize.
Changing from 0 to 1 generates a Card Insertion interrupt in the Normal Interrupt
Address
0X4AC00024 RO/ROC Present State Register (Channel 0)
RO/ROC Present State Register (Channel 1)
0X4A800024
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
R/W Description
Description
HSMMC CONTROLLER
Reset Value
0x000A0000
0x000A0000
Initial
Value
0
0
Line
State
1
Line
State
1
(After
Reset)
0
21-29