Samsung S3C2451X User Manual page 389

S3C2451X RISC MICROPROCESSOR
EP0 CONTROL REGISTER (EP0CR)
EP0 control register is used for the control of endpoint 0. Controls such as enabling ep0 related interrupts and
toggle controls can be handled by EP0 control register.
Register Address
EP0CR 0x4980_0028
EP0CR Bit
[31:2]
ESS [1]
TZLS [0]
R/W
R/W EP0 Control Register
R/W
Reserved
R/W Endpoint Stall Set
ESS is set by MCU when it intends to send STALL
handshake to Host. This bit is cleared when the MCU writes
0 on it.
ESS is needed to be set 0 after MCU writes 1 on it.
R/W Tx Zero Length Set.
TZLS is set by MCU when it intends to send Tx zero length
data to Host.
TZLS is useful for core Test.
TZLS can be managed when Tx Test Enable (TTE) bit is
set.
This bit is cleared when the MCU writes 0 on it
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
USB2.0 DEVICE
Reset Value
0x0
Initial State
0
0
17-17