Samsung S3C2451X User Manual page 310

WATCHDOG TIMER
WATCHDOG TIMER OPERATION
BLOCK DIAGRAM
Figure 12-1 shows the functional block diagram of the watchdog timer. The watchdog timer uses only PCLK as its
source clock. The PCLK frequency is prescaled to generate the corresponding watchdog timer clock, and the
resulting frequency is divided again.
8-bit Prescaler
PCLK
WTCON[15:8]
The prescaler value and the frequency division factor are specified in the watchdog timer control (WTCON)
register. Valid prescaler values range from 0 to 28-1. The frequency division factor can be selected as 16, 32, 64,
or 128.
Use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock
cycle:
WTDAT & WTCNT
Watchdog Timer operation based on the value of watchdog timer count (WTCNT) register. Once timer is
operated, count value will be down counting from the initial value of WTCNT register. During the watchdog timer
operation, it contains the current count values.
The value of WDTAT register will be automatically reloaded into WTCNT at every time-out, if watchdog timer is
used for the normal timer.
Note : At initial watchdog timer operation(of enable), the value of watchdog timer data (WTDAT) register is not
automatically loaded into the timer counter (WTCNT). An initial value MUST be written to the watchdog timer
count (WTCNT) register, before the watchdog timer starts.
CONSIDERATION OF DEBUGGING ENVIRONMENT
When the S3C2451X is in debug mode using Embedded ICE, the watchdog timer must not operate.
The watchdog timer can determine whether or not it is currently in the debug mode from the CPU core signal
(DBGACK signal). Once the DBGACK signal in CPU core is asserted, the reset output of the watchdog timer is
not activated as the watchdog timer is expired.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
12-2
Specifications and information herein are subject to change without notice.
MUX
1/16
1/32
1/64
1/128
WTCON[4:3]
Figure 12-1. Watchdog Timer Block Diagram
t_watchdog = 1 / [ PCLK / (Prescaler value + 1) / Division_factor ]
S3C2451X RISC MICROPROCESSOR
WTDAT
WTCNT
(Down Counter)
WTCON[2]
Interrupt
Reset Signal Generator
WTCON[0]
RESET