Samsung S3C2451X User Manual page 150

NAND FLASH CONTROLLER
7.3 BLOCK DIAGRAM
AHB
Slave I/F
7.4 BOOT LOADER FUNCTION
CORE ACCESS
(Boot Code)
USER ACCESS
During reset, the IROM gets the information about the adopted NAND flash memory by using the pin status of
GPC5/6/7 (refer to PIN CONFIGURATION). In case of POR(Power-On-Reset) or system reset, the IROM
automatically loads the 8-KB boot-loader codes into the steppingstone(0x40000000). After finishing the migration
of the boot-loader codes, the codes in steppingstone will be executed.
In case of IROM boot mode, the ECC-checking for boot-loader code will be done. Therefore, 0 block of
NAND flash should be valid block by 8Bit ECC.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
7-2
Specifications and information herein are subject to change without notice.
SFR
Figure 7-1. NAND Flash Controller Block Diagram
REGISTERS
Stepping Stone
(64KB Buffer)
Special Function
Registers
Figure 7-2. NAND Flash Controller Boot Loader Block Diagram
ECC Gen.
Control &
State Machine
Stepping Stone
Controller
AUTO BOOT
NAND FLASH
Controller
NOTE:
S3C2451X RISC MICROPROCESSOR
nFCE
CLE
ALE
NAND FLASH
nRE
Interface
nWE
RnB
I/O0 - I/O7
Stepping Stone
(64KB SRAM)
NAND FLASH
Memory