Samsung S3C2451X User Manual page 398

USB2.0 DEVICE
DMA CONTROL REGISTER (DCR)
The AHB Master Operation is controlled by the programming DMA Control Register and DMA IF Control Register.
Register Address
DCR 0x4980_0040
DCR Bit
[31:6]
ARDRD [5]
FMDE [4]
DMDE [3]
TDR [2]
RDR [1]
DEN [0]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
17-26
Specifications and information herein are subject to change without notice.
R/W
R/W DMA Control Register
R/W
Reserved
R/W Auto Rx DMA Run set disable.
0 = set
1 = disable
This bit is cleared when DMA operation is ended.
R/W Burst Mode Enable.
This bit is used to run Burst Mode DMA Operation.
0 = Burst mode disable
1 = Burst mode enable
Demand Mode DMA Enable.
R/W
This bit is used to run Demand mode DMA operation.
0: Demand mode disable.
1: Demand mode enable.
R/W Tx DMA Operation Run
This bit is used to set start DMA operation for Tx Endpoint
(IN endpoint)
0 = DMA operation stop
1 = DMA operation run
R/W Rx DMA Operation Run
This bit is used to start DMA operation for Rx Endpoint
(OUT endpoint).
This bit is automatically set when USB receives OUT packet
data and DEN bit is set to 1 and ARDRD bit is set to 0.
To operate DMA operation after OUT packet data received,
MCU must set RDR to 1.
0 = DMA operation stop.
1 = DMA operation run.
R/W DMA Operation Mode Enable
This bit is used to set the DMA Operation mode
0 = Interrupt Operation mode
1 = DMA Operation mode
S3C2451X RISC MICROPROCESSOR
Description
Description
Reset Value
0x0
Initial State
0
0
0
0
0
0