Samsung S3C2451X User Manual page 464

HS_SPI CONTROLLER
HS_SPI_INT_EN
IntEnTrailing
IntEnRxOverrun
IntEnRxUnderrun
IntEnTxOverrun
IntEnTxUnderrun
IntEnRxFifoRdy
IntEnTxFifoRdy
Register
HS_SPI_STATUS(Ch0)
HS_SPI_STATUS(Ch1)
HS_SPI_STATUS
TX_done
Trailing_count_done
RxFifoLvl
TxFifoLvl
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
20-8
Specifications and information herein are subject to change without notice.
Bit
Interrupt Enable for trailing count to be zero
[6] R/W
0: Disable
R/W
[5]
0: Disable
R/W
[4]
0: Disable
R/W
[3]
0: Disable
Interrupt Enable for TxUnderrun. In slave
mode, this bit should be clear first after turning
R/W
on slave TX path.
[2]
0: Disable
Interrupt Enable for RxFifoRdy(INT mode)
R/W
[1]
0: Disable
Interrupt Enable for TxFifoRdy(INT mode)
R/W
[0]
0: Disable
Address R/W
0x52000014 R
0x59000014 R
Bit
Indication of transfer done in Shift register
0 : all case except blow case
[21] R
1 : when tx fifo and shift register are empty
*Master mode only
[20] R Indication that trailing count is zero
Data level in RX FIFO
R
[19:13]
0 ~ 7'h40 byte
Data level in TX FIFO
R
[12:6]
Description
Interrupt Enable for RxOverrun
Interrupt Enable for RxUnderrun
Interrupt Enable for TxOverrun
Description
HS_SPI status register
HS_SPI status register
Description
S3C2451X RISC MICROPROCESSOR
Initial State
1:Enable
1:Enable
1:Enable
1:Enable
1:Enable
1:Enable
1:Enable
Reset Value
Initial State
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
0x0
0x0
1'b0
1'b0
7'b0
7'b0