Samsung S3C2451X User Manual page 459

S3C2451X RISC MICROPROCESSOR
FIFO ACCESS
The HS_SPI in S3C2451x supports CPU access and DMA access to FIFOs. Data size of CPU access and DMA
access to FIFOs can be selected 8-bit/16-bit/32-bit data. If 8-bit data size is chosen, valid bits are from 0 bit to 7
bit. CPU accesses are normally on and off by trigger threshold user defines. The trigger level of each FIFOs is set
from 0byte to 64bytes. TxDMAOn or RxDMAOn bit of HS_SPI_MODE_CFG register should be set to use DMA
access. DMA access supports only single transfer and 4-burst transfer. In TX FIFO, dma request signal is high
until that FIFO is full. In RX FIFO, dma request signal is high if FIFO is not empty.
TRAILING BYTES IN THE RX FIFO
When the number of samples in Rx FIFO is less than the threshold value in INT mode or DMA 4 burst mode and
no additional data is received, the remaining bytes are called trailing bytes. To remove these bytes in RX FIFO,
internal timer and interrupt signal are used. The value of internal timer can be set up to 1024 clocks based on
APB BUS clock. When timer value is to be zero, interrupt signal is occurred and CPU can remove trailing bytes in
FIFO.
PACKET NUMBER CONTROL
HS_SPI can control the number of packets to be received in master mode. If there is any number of packets to be
received, just set the SFR(Packet_Count_reg) how many packets have to be received. HS_SPI stops generating
HS_SPICLK when the number of packets is the same as what you set. But, software reset or hardware reset
should be followed before that this function is reload.
NCS CONTROL
nCS can be selected auto control or manual control. In manual control, Auto_n_Manual should be set default
value 0. nCS level is decided as the same as that nSSout bit is set. nCS can be toggled between packet and
packet in auto control. Auto_n_Manual is set to 1 and nCS_time_count should be set as long as nCS is inactive.
nSSout is not available at this time.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
HS_SPI CONTROLLER
20-3