Samsung S3C2451X User Manual page 350

UART
BLOCK DIAGRAM
Peripheral BUS
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
15-2
Specifications and information herein are subject to change without notice.
Transmitter
Transmit Buffer
Register(64 Byte)
Transmit Shifter
Control Buad-rate
Unit Generator
Receiver
Receive Shifter
Receive Buffer
Register(64 Byte)
In FIFO mode, all 64 Byte of Buffer register are used as FIFO register.
In non-FIFO mode, only 1 Byte of Buffer register is used as Holding register.
Figure 15-1. UART Block Diagram (with FIFO)
S3C2451 RISC MICROPROCESSOR
Transmit FIFO Register
(FIFO mode)
Transmit Holding Register
(Non-FIFO mode)
Clock Source
(PCLK, FCLK/n,UEXTCLK)
Receive Holding Register
(Non-FIFO mode only)
Receive FIFO Register
(FIFO mode)
TXDn
RXDn