Samsung S3C2451X User Manual page 519

S3C2451X RISC MICROPROCESSOR
ERROR INTERRUPT STATUS ENABLE REGISTER
Setting to 1 enables Error Interrupt Status.
Register
ERRINTSTSEN0
ERRINTSTSEN1
Name Bit
[15:10]
ADMAER [9]
R
ENSTAAC [8]
MDERR
ENSTACU [7]
RERR
ENSTADE [6]
NDERR
ENSTADA [5]
TCRCER
R
ENSTADA [4]
TTOUTER
R
ENSTAC [3]
MDIDXER
R
ENSTAC [2]
MDEBITE
RR
ENSTAC [1]
MDCRCE
RR
ENSTAC [0]
MDTOUT
ERR
Address
0X4AC00036
0X4A800036
Reserved
ADMA Error Status Enable
'1' = Enabled
'0' = Masked
Auto CMD12 Error Status Enable
'1' = Enabled
'0' = Masked
Current Limit Error Status Enable
This function is not implemented in this version.
'1' = Enabled
'0' = Masked
Data End Bit Error Status Enable
'1' = Enabled
'0' = Masked
Data CRC Error Status Enable
'1' = Enabled
'0' = Masked
Data Timeout Error Status Enable
'1' = Enabled
'0' = Masked
Command Index Error Status Enable
'1' = Enabled
'0' = Masked
Command End Bit Error Status Enable
'1' = Enabled
'0' = Masked
Command CRC Error Status Enable
'1' = Enabled
'0' = Masked
Command Timeout Error Status Enable
'1' = Enabled
'0' = Masked
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
R/W Description
R/W Error Interrupt Status Enable
Register (Channel 0)
R/W Error Interrupt Status Enable
Register (Channel 1)
Description
HSMMC CONTROLLER
Reset Value
0x0
0x0
Initial Value
0
0
0
0
0
0
0
0
0
0
0
21-51