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S3C2451X RISC MICROPROCESSOR
IIS MODE REGISTER (IISMOD)
Register
IISMOD
IISMOD
BLC
CDCLKCON
IMS
TXR
LRP
SDF
RFS
Address
0x55000104
Bit
R/W
[31:15]
R/W
Reserved. Program to zero.
[14:13]
R/W
Bit Length Control Bit Which decides transmission of 8/16 bits per
audio channel
00:16 Bits per channel
01:8 Bits Per Channel
10:24 Bits Per Channel
11:Reserved
[12]
R/W
Determine direction of codec clock(I2SCDCLK)
0 : Supply codec clock to external codec chip.
(from PCLK, EPLL, EPLLRefCLK)
1 : Get codec clock from external codec chip.
(to CLKAUDIO)
(Refer to Figure 25-2)
[11:10]
R/W
IIS master or slave mode select. (and select source of codec clock)
00: Master mode
01: Master mode
(CLKAUDIO is source clock for I2SSCLK, I2SLRCLK.
10: Slave mode
11: Slave mode
(Refer to Figure 25-2)
[9:8]
R/W
Transmit or receive mode select.
00: Transmit only mode
01: Receive only mode
10: Transmit and receive simultaneous mode
11: Reserved
[7]
R/W
Left/Right channel clock polarity select.
0: Low for left channel and high for right channel
1: High for left channel and low for right channel
[6:5]
R/W
Serial data format.
00: IIS format
01: MSB-justified (left-justified) format
10: LSB-justified (right-justified) format
11: Reserved
[4:3]
R/W
IIS root clock (codec clock) frequency select.
00: 256 fs, where fs is sampling frequency
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
IIS interface mode register
(PCLK is source clock for I2SSCLK, I2SLRCLK, I2SCDCLK)
CLKAUDIO-EPLL, EPLLRefCLK is source clock for I2SCDCLK)
(PCLK is source clock for I2SCDCLK)
(CLKAUDIO-EPLL, EPLLRefCLK is source clock for I2SCDCLK)
Description
IIS-BUS INTERFACE
Reset Value
0x0000_0000
25-17
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