Samsung S3C2451X User Manual page 462

HS_SPI CONTROLLER
RxChOn
TxChOn
Register
Clk_CFG(Ch0)
Clk_CFG(Ch1)
Clk_CFG
ClkSel [10:9]
ENCLK
Prescaler [7:0]
Value
Register
MODE_CFG(Ch0)
MODE_CFG(Ch1)
MODE_CFG
Ch_tran_size
Trailing Count
BUS transfer size
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
20-6
Specifications and information herein are subject to change without notice.
R/W HS_SPI Rx Channel On
[1]
0: Channel Off
R/W HS_SPI Tx Channel On
[0]
0: Channel Off
Address R/W
0x52000004 R/W
0x59000004 R/W
Bit
R/W Clock source selection to generate HS_SPI clock-
out
00 : PCLK
10 : Epll clock
*
For using USBCLK source, The USB_SIG_MASK at
system controller should be set to on..
*Epll clock is from System Controller and has 4 sources:
MOUT
R/W
[8] Clock on/off
0 : disable
R/W
HS_SPI clock-out division rate
HS_SPI clock-out =
Address R/W
0x52000008 R/W
0x59000008 R/W
Bit
[30:29] R/W
[28:19] R/W
[18:17] R/W
1: Channel On
1: Channel On
Description
Clock configuration register
Clock configuration register
Description
01 : USBCLK
11 : reserved
, DOUT , PLL_SRCLK, CLK27M
EPLL MPLL
Clock source / ( 2 x (Prescaler value +1))
Description
HS_SPI FIFO control register
HS_SPI FIFO control register
Description
00 : Byte
10 : word
Count value from writing the last data in RX
FIFO to flush trailing bytes in FIFO
00: byte
10 : word
S3C2451X RISC MICROPROCESSOR
1 : enable
01 : Halfword
11 : reserved
01: halfword
11:reserved
1'b0
1'b0
Reset Value
0x0
0x0
Initial State
2'b0
1'b0
8'h0
Reset Value
0x0
0x0
Initial State
2'b0
10'b0
2'b0