Samsung S3C2451X User Manual page 631

S3C2451X RISC MICROPROCESSOR
CODEC CAPTURE SEQUENCE REGISTER
Register
CICOCPTSEQ 0x4D80_00A4
CICOCPTSEQ
Cpt_CoDMA_Seq
31 30
1 1
Capture Capture
•
For skipped frmes, IRQ_CI_c is not generated. And FrameCnt_co is not increased
Address R/W
RW
Bit
[31:0] Capture sequence pattern in Codec DMA
29
0
No
Capture
Figure 23-19 Capture codec dma frame control
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Codec dma capture sequence related
Description
Cpt_CoDMA_Seq[31:0]
. . . . . .
Repeat
CAMERA INTERFACE
Reset Value
0xFFFFFFFF
Initial State
0xFFFF_FFF
F
Cpt_CoDMA_Ptr
1
1 0
Capture
0
1
23-39