Samsung S3C2451X User Manual page 297

S3C2451X RISC MICROPROCESSOR
EINTFLTn (External Interrupt Filter Register n)
To recognize the level interrupt, the valid logic level on EXTINTn pin must be retained for 40ns at least because of
the noise filter.
Register
EINTFLT0
EINTFLT1
EINTFLT2
EINTFLT3
EINTFLT2
FLTCLK19
EINTFLT19
FLTCLK18
EINTFLT18
FLTCLK17
EINTFLT17
FLTCLK16
EINTFLT16
EINTFLT3
FLTCLK23
EINTFLT23
FLTCLK22
EINTFLT22
FLTCLK21
EINTFLT21
FLTCLK20
EINTFLT20
Address R/W
0x56000094 R/W
0x56000098 R/W
0x5600009c R/W
0x4c6000a0 R/W
Bit
[31] Filter clock of EINT19 (configured by OM)
0 = PCLK
[30:24] Filtering width of EINT19
[23] Filter clock of EINT18 (configured by OM)
0 = PCLK
[22:16] Filtering width of EINT18
[15] Filter clock of EINT17 (configured by OM)
0 = PCLK
[14:8] Filtering width of EINT17
[7] Filter clock of EINT16 (configured by OM)
0 = PCLK
[6:0] Filtering width of EINT16
Bit
[31] Filter clock of EINT23 (configured by OM)
0 = PCLK
[30:24] Filtering width of EINT23
[23] Filter clock of EINT22 (configured by OM)
0 = PCLK
[22:16] Filtering width of EINT22
[15] Filter clock of EINT21(configured by OM)
0 = PCLK
[14:8] Filtering width of EINT21
[7] Filter clock of EINT20 (configured by OM)
0 = PCLK
[6:0] Filtering width of EINT20
Description
Reserved
Reserved
External interrupt control register 2
External interrupt control register 3
Description
1= EXTCLK/OSC_CLK
1= EXTCLK/OSC_CLK
1= EXTCLK/OSC_CLK
1= EXTCLK/OSC_CLK
Description
1= EXTCLK/OSC_CLK
1= EXTCLK/OSC_CLK
1= EXTCLK/OSC_CLK
1= EXTCLK/OSC_CLK
I/O PORTS
Reset Value
0x0
0x0
0x0
0x0
11-41