Samsung S3C2451X User Manual page 388

USB2.0 DEVICE
EP0 STATUS REGISTER (EP0SR)
This register stores status information of the Endpoint 0. These status information are set automatically by the
core when corresponding conditions are met. After reading the bits, MCU should write 1 to clear them.
Register Address
EP0SR 0x4980_0024
EP0SR Bit
[31:7]
LWO [6]
[5]
SHT [4]
[3:2]
TST [1]
RSR [0]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
17-16
Specifications and information herein are subject to change without notice.
R/W
R/W EP0 Status Register
R/W
Reserved
R Last Word Odd
LWO informs that the last word of a packet in FIFO has an
invalid upper byte. This bit is cleared automatically after the
MCU reads it from the FIFO.
Reserved
R/C Stall Handshake Transmitted
SHT informs that STALL handshake due to stall condition is
sent to Host. This bit is an interrupt source. This bit is
cleared when the MCU writes 1.
Reserved
R/C Tx successfully received
TST is set by core after core sends TX data to Host and
receives ACK successfully. TST is one of the interrupt
sources.
R/C Rx successfully received.
RSR is set by core after core receives error free packet from
Host and sent ACK back to Host successfully. RSR is one of
the interrupt sources.
S3C2451X RISC MICROPROCESSOR
Description
Description
Reset Value
0x0
Initial State
0
0
0
0