Samsung S3C2451X User Manual page 103

S3C2451X RISC MICROPROCESSOR
USB PHY CONTROL REGISTER (PHYCTRL)
Register
PHYCTRL 0x4C00_0080
PHYCTRL
RESERVED
CLK_SEL
EXT_CLK
INT_PLL_SEL
DOWNSTREAM_
PORT
Address R/W
R/W
Bit
[31:5] -
[4:3] Reference Clock Frequency Select
00 = 48MHz
01 = Reserved
10 = 12MHz
11 = 24MHz
[2] Clock Select for XO Block
0 = Crystal
1 = Oscillator
[1] Host 1.1 uses Internal PLL Clock (48MHz)
0 = System PLL Clock (USBHOSTCLK should be 48MHz and
The CLK_SEL[1:0] bus must be set to 2'b00)
1 = USB Internal PLL Clock
[0] Downstream Port Select
0 = Device (Function) Mode
1 = Host Mode
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
USB2.0 PHY Control Register
Description
SYSTEM CONTROLLER
Reset Value
0x0000_0000
Initial State
0
2'b00
0
0
0
2-37