Samsung S3C2451X User Manual page 227

S3C2451X RISC MICROPROCESSOR
10
OVERVIEW
The interrupt controller in the S3C2451X receives the request from 59 interrupt sources. These interrupt sources
are provided by internal peripherals such as the DMA controller, the UART, IIC, and others. In these interrupt
sources, the UARTn and EINTn interrupts are 'OR'ed to the interrupt controller.
When receiving multiple interrupt requests from internal peripherals and external interrupt request pins, the
interrupt controller requests FIQ or IRQ interrupt of the ARM926EJ core after the arbitration procedure.
The arbitration procedure depends on the hardware priority logic and the result is written to the interrupt pending
register, which helps users notify which interrupt is generated out of various interrupt sources.
Request sources
(with sub -register)
Request sources
(without sub -register)
INTERRUPT CONTROLLER
SUBSRCPND SUBMASK
Figure 10-1. Interrupt Process Diagram
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
SRCPND MASK
MODE
INTERRUPT CONTROLLER
INTPND
Priority IRQ
FIQ
10-1