Samsung S3C2451X User Manual page 116

STATIC MEMORY CONTROLLER
ASYNCHRONOUS READ
Figure 5-3 shows an external memory read transfer with two output enable delay states, WSTOEN = 2, and two
wait states, WSTRD = 2. Four AHB wait states are inserted during the transfer, two for the standard read, and
additional two because of the programmed wait states added.
The PSMAVD signal might be required for synchronous static memory devieces when you use it in asynchronous
mode. You can disable this using the AddrValidReadEn bit in the SMBCRx register. This bit defaults to being set
(enable) to enable a system to boot from synchronous memory. You can then clear it if you do not require it.
When disabled, the signal is driven HIGH continuously.
Asynchronous Read
SMCLK
ADDR
DATA(IN)
nCS
nOE
Figure 5-3. External Memory Two Output Enable Delay State Read
SMCLK
ADDR
nCS
nOE
nWAIT
DATA ( R )
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
5-4
Specifications and information herein are subject to change without notice.
Figure 5-4. Read Timing diagram (DRnCS = 1, DRnOWE = 0)
WSTRD=2
WSTOEN=2
A
S3C2451X RISC MICROPROCESSOR
A
D(A)
D(A)