Samsung S3C2451X User Manual page 127

S3C2451X RISC MICROPROCESSOR
BANK WRITE WAIT STATE CONTROL REGISTERS 0-5
Register
SMBWSTWRR0 0x4F000008
SMBWSTWRR1 0x4F000028
SMBWSTWRR2 0x4F000048
SMBWSTWRR3 0x4F000068
SMBWSTWRR4 0x4F000088
SMBWSTWRR5 0x4F0000A8
[31:5]
WSTWR [4:0]
BANK OUTPUT ENABLE ASSERTION DELAY CONTROL REGISTERS 0-5
Register
SMBWSTOENR0 0x4F00000C
SMBWSTOENR1 0x4F00002C
SMBWSTOENR2 0x4F00004C
SMBWSTOENR3 0x4F00006C
SMBWSTOENR4 0x4F00008C
SMBWSTOENR5
WSTOEN
NOTE: If you would use a muxed OneNAND, the regiseter value of WSTOEN should be larger than 2.
Address R/W
R/W Bank0 write wait state control register
R/W Bank1 write wait state control register
R/W Bank2 write wait state control register
R/W Bank3 write wait state control register
R/W Bank4 write wait state control register
R/W Bank5 write wait state control register
Bit
Read undefined. Write as zero.
Write wait state. Defaults to 11111 at reset.
For SRAM , the WSTWR field controls the number of wait states
for write accesses, and the external wait assertion timing for
writes.
Wait state time = WSTWR x SMCLK period
WSTWR does not apply to read-only devices such as ROM.
Address R/W
R/W Bank0 output enable assertion delay control register
R/W Bank1 output enable assertion delay control register
R/W Bank2 output enable assertion delay control register
R/W Bank3 output enable assertion delay control register
R/W Bank4 output enable assertion delay control register
0x4F0000A R/W Bank5 output enable assertion delay control register
C
Bit
[31:4] Read undefined. Write as zero.
[3:0] Output enable assertion delay from chip select assertion.
Default to 0x2 at reset
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
Description
Description
STATIC MEMORY CONTROLLER
Reset Value
0x1F
0x1F
0x1F
0x1F
0x1F
0x1F
Initial State
0x0
0x1F
Reset Value
0x2
0x2
0x2
0x2
0x2
0x2
Initial State
0x0
0x2
5-15