Samsung S3C2451X User Manual page 42

PRODUCT OVERVIEW
Register Name
SMBWSTOENR3
SMBWSTOENR4
SMBWSTOENR5
SMBWSTWENR0
SMBWSTWENR1
SMBWSTWENR2
SMBWSTWENR3
SMBWSTWENR4
SMBWSTWENR5
SMBCR0
SMBCR1
SMBCR2
SMBCR3
SMBCR4
SMBCR5
SMBSR0
SMBSR1
SMBSR2
SMBSR3
SMBSR4
SMBSR5
SMBWSTBRDR0
SMBWSTBRDR1
SMBWSTBRDR2
SMBWSTBRDR3
SMBWSTBRDR4
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
1-38
Specifications and information herein are subject to change without notice.
Address Reset Value
0x4F00006C 0x00000002
0x4F00008C 0x00000002
0x4F0000AC 0x00000002
0x4F000010 0x00000002
0x4F000030 0x00000002
0x4F000050 0x00000002
0x4F000070 0x00000002
0x4F000090 0x00000002
0x4F0000B0 0x00000002
0x4F000014
0x4F000034 0x00303000
0x4F000054 0x00303010
0x4F000074 0x00303000
0x4F000094 0x00303010
0x4F0000B4 0x00303010
0x4F000018 0x00000000
0x4F000038 0x00000000
0x4F000058 0x00000000
0x4F000078 0x00000000
0x4F000098 0x00000000
0x4F0000B8 0x00000000
0x4F00001C 0x0000001F
0x4F00003C 0x0000001F
0x4F00005C 0x0000001F
0x4F00007C 0x0000001F
0x4F00009C 0x0000001F
Acc. Read/
Unit Write
W R/W
W R/W
W R/W
W R/W
W R/W
W R/W
W R/W
W R/W
W R/W
- W R/W
W R/W
W R/W
W R/W
W R/W
W R/W
W R/W
W R/W
W R/W
W R/W
W R/W
W R/W
W R/W
W R/W
W R/W
W R/W
W R/W
S3C2451X RISC MICROPROCESSOR
Function
Bank3 output enable assertion delay
control register
Bank4 output enable assertion delay
control register
Bank5 output enable assertion delay
control register
Bank0 write enable assertion delay
control register
Bank1 write enable assertion delay
control register
Bank2 write enable assertion delay
control register
Bank3 write enable assertion delay
control register
Bank4 write enable assertion delay
control register
Bank5 write enable assertion delay
control register
Bank0 control register
Bank1 control register
Bank2 control register
Bank3 control register
Bank4 control register
Bank5 control register
Bank0 status register
Bank1 status register
Bank2 status register
Bank3 status register
Bank4 status register
Bank5 status register
Bank0 burst read wait delay control
register
Bank1 burst read wait delay control
register
Bank2 burst read wait delay control
register
Bank3 burst read wait delay control
register
Bank4 burst read wait delay control
register