Samsung S3C2451X User Manual page 681

S3C2451X RISC MICROPROCESSOR
RX CHANNEL
The I2S RX channel provides a single stereo compliant output. The receive channel can operate in master or
slave mode. Data is received from the input line and transferred into the RX FIFO. The processor can then
read this data via an APB read or a DMA access can access this data.
RX Channel has a 16X32 bit wide RX FIFO where the processor or DMA can read upto 16 left/right data
samples after enabling the channel for reception.
An Example sequence is as following.
Ensure the PCLK and CLKAUDIO are coming correctly to the I2S controller and FLUSH the RX FIFO using
the RFLUSH bit in the I2SFIC Register (I2S FIFO Control Register) and the I2S controller is configured in
any of the modes
•
Receive only.
•
Receive/Transmit simultaneous mode
This can be done by Programming the TXR bit in the I2SMOD Register (I2S Mode Register)
1. Then Program the following parameters according to the need
•
IMS
•
SDF
•
BFS
•
BLC
•
LRP
For Programming, the above mentioned fields please refer I2SMOD Register (I2S Mode Register)
2. Once ensured that the input clocks for I2S controller are up and running and step 1 and 2 have been
completed user must put the I2SACTIVE high to enable any reception of data, the I2S Controller
receives data on the LRCLK change.
The Data must be read from the RX FIFO using the I2SRXD Register (I2S RX FIFO Register) only after
looking
at the RX FIFO count in the I2SFIC Register (I2S FIFO Control Register). The count would only increment
once the complete left channel and right have been received.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
IIS MULTI AUDIO INTERFACE
26-11