Samsung S3C2451X User Manual page 508

HSMMC CONTROLLER
CLOCK CONTROL REGISTER
At the initialization of the Host Controller, the Host Driver shall set the SDCLK Frequency Select according to the
Capabilities register.
Register
CLKCON0
CLKCON1
Name Bit
[15:8] SDCLK Frequency Select
SELFRE
This register is used to select the frequency of SDCLK pin. The frequency is not
Q
programmed directly; rather this register holds the divisor of the Base Clock
Frequency For SD Clock in the Capabilities register. Only the following settings
are allowed.
80h
40h
20h
10h
08h
04h
02h
01h
00h
Setting 00h specifies the highest frequency of the SD Clock. When setting multiple
bits, the most significant bit is used as the divisor. But multiple bits should not be
set. The two default divider values can be calculated by the frequency that is
defined by the Base Clock Frequency For SD Clock in the Capabilities register.
(1) 25MHz divider value
(2) 400KHz divider value
According to the SD Physical Specification Version 1.01 and the SDIO Card
Specification Version 1.0, maximum SD Clock frequency is 25MHz, and shall never
exceed this limit.
The frequency of SDCLK is set by the following formula:
Clock Frequency = (Base Clock) / divisor
Thus, choose the smallest possible divisor which results in a clock frequency that
is less than or equal to the target frequency.
For example, if the Base Clock Frequency For SD Clock in the Capabilities
register has the value 33MHz, and the target frequency is 25MHz, then choosing
the divisor value of 01h will yield 16.5MHz, which is the nearest frequency less than
or equal to the target. Similarly, to approach a clock value of 400KHz, the divisor
value of 40h yields the optimal clock value of 258KHz.
[7:4] Reserved
External Clock Stable
STBLEX [3]
This bit is set to 1 when SD Clock output is stable after writing to SD Clock
TCLK
Enable in this register to 1. The SD Host Driver shall wait to issue command to
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-40
Specifications and information herein are subject to change without notice.
Address
0X4AC0002C
0X4A80002C
base clock divided by 256
base clock divided by 128
base clock divided by 64
base clock divided by 32
base clock divided by 16
base clock divided by 8
base clock divided by 4
base clock divided by 2
base clock (10MHz-63MHz)
R/W
R/W Command Register (Channel 0)
R/W Command Register (Channel 1)
Description
S3C2451X RISC MICROPROCESSOR
Description Reset Value
0x0
0x0
Initial
Value
0
0