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S3C2451X RISC MICROPROCESSOR
HOST TO SCREEN CONTINUE BitBLT REGISTER (CMD3_REG)
Register
CMD3_REG
0x4D40810C
Field
Bit
Data
[31:0]
HOST TO SCREEN START COLOR EXPANSION REGISTER (CMD4_REG)
Register
CMD4_REG
0x4D408110
Field
Bit
Data
[31:0]
HOST TO SCREEN CONTINUE COLOR EXPANSION REGISTER (CMD5_REG)
Register
CMD5_REG
0x4D408114
Field
Bit
Data
[31:0]
MEMORY TO SCREEN COLOR EXPANSION REGISTER (CMD7_REG)
Register
CMD7_REG
0x4D40811C
Field
Bit
Memory
[31:0]
Address
bpp (e.g., RGB565), the upper 16 bits of the data are ignored.
Address
R/W
W
Host to Screen Continue BitBLT Register
BitBLT data (Continue)
Note that the data written to this register represents only one pixel,
regardless of the source color mode. If the source color mode is 16-
bpp (e.g., RGB565), the upper 16 bits of the data are ignored.
Address
R/W
W
Host to Screen Start Color Expansion Register
Color Expansion Data (Start)
Address
R/W
W
Host to Screen Continue Color Expansion Register
Color Expansion Data (Continue)
Address
R/W
W
Memory to Screen Color Expansion Register
Bitmap data base address (used in memory-to-screen mode, should
be word-aligned).
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
Description
Description
Description
Description
Description
Description
2D
Reset Value
0x0
Initial State
-
Reset Value
0x0
Initial State
-
Reset Value
0x0
Initial State
-
Reset Value
0x0
Initial State
-
19-19
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