Samsung S3C2451X User Manual page 111

S3C2451X RISC MICROPROCESSOR
4
BUS PRIORITIES
OVERVIEW
The bus arbitration logic determines the priorities of bus masters. It supports a combination of rotation priority
mode and fixed priority mode.
BUS PRIORITY MAP
The S3C2451 holds 16 masters on the AHB_S(System Bus), 9 masters on the AHB_I(Image Bus) and 9masters
on the APB Bus. The following list shows the priorities among these bus masters after a reset.
Priority AHB_S BUS MASTERS
0
1
2
3
4
5
6
7
8
9
10
11 UDEVICE20
12
10
11
13 ARM926EJ DBUS
14 ARM926EJ IBUS
15
CF 1. Fix Type: all priority can be changed according to register value
stored in The System Controller.
HS-MMC1
DMA0
2 Rotation Type: all masters' priority can be rotatable according to
DMA1
register value stored in The System Controller.
DMA2
(Except for Default Masters)
DMA3
DMA4
DMA5
DMA6
DMA7
UHOST
HS-MMC0
Reserved
Reserved
Default
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Comment
BUS PRIORITIES
4-1