Samsung S3C2451X User Manual page 518

HSMMC CONTROLLER
ENSTABUFR
[5]
DRDY
ENSTABUF
[4]
WTRDY
[3]
ENSTADMA
ENSTABLKG
[2]
AP
ENSTASTAN
[1]
SCMPLT
ENSTACMD
[0]
CMPLT
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-50
Specifications and information herein are subject to change without notice.
Buffer Read Ready Status Enable
'1' = Enabled
'0' = Masked
Buffer Write Ready Status Enable
'1' = Enabled
'0' = Masked
DMA Interrupt Status Enable
'1' = Enabled
'0' = Masked
Block Gap Event Status Enable
'1' = Enabled
'0' = Masked
Transfer Complete Status Enable
'1' = Enabled
'0' = Masked
Command Complete Status Enable
'1' = Enabled
'0' = Masked
S3C2451X RISC MICROPROCESSOR
0
0
0
0
0
0