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S3C2451X RISC MICROPROCESSOR
EPLLCON
RESERVED
EPLLEN_STOP
ONOFF
MDIV
RESERVED
PDIV
RESERVED
SDIV
EPLLCON_K
RESERVED
KDIV
The output frequencies of EPLL can be calculated using the following equations:
)× FIN) / (p × 2
16
F
= ((m+k/2
OUT
Fvco = (m x F
) / p
IN
where, m = MDIV, p = PDIV, s =SDIV, k = KDIV Fin = 10~40MHz
Don't set the value PDIV[5:0] or MDIV[7:0] to all zeros. (6'b00 0000 / 8'b0000 0000)
Although there is the equation for choosing PLL value, we strongly recommend only the values in the PLL
value recommendation table. If you have to use other values, please contact us.
FIN
(MHz)
12
12
12
12
12
12
Bit
[31:26]
-
[25]
EPLL ON/OFF in STOP mode. 0:OFF, 1:ON
[24]
EPLL ON/OFF. 0:ON, 1:OFF
[23:16]
EPLL main divider value
[15:14]
-
[13:8]
EPLL pre-divider value
[7:3]
-
[2:0]
EPLL post-scaler value
Bit
[31:16]
-
[15:0]
EPLL fractional modulator
s
) (should be 20~600MHz)
FOUT
MDIV
(MHz)
(decimal)
36
48
48
32
60
40
72
48
84
28
96
32
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
NOTE:
PDIV
SDIV
(decimal)
(decimal)
1
4
1
3
1
3
1
3
1
2
1
2
SYSTEM CONTROLLER
Initial Value
0x00
0
1
0x20
0x0
0x1
0x00
0x2
Initial Value
0
0x0000
KDIV
Error
(decimal)
[MHz]
0
0
0
0
0
0
0
0
0
0
0
0
2-23
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