Samsung S3C2451X User Manual page 144

MOBILE DRAM CONTROLLER
MOBILE DRAM (EXTENDED ) MODE REGISTER SET REGISTER
Register
BANKCON3
1) mSDRAM / mDDR
PnBANKCON
BA [31:30]
Reserved [29:23]
DS [22:21]
Reserved [20:19]
PASR [18:16]
BA [15:14]
Reserved [15:7]
CAS Latency [6:4]
Burst Type
Burst Length [2:0]
Note: Bit[15:0] is used for MRS command cycle, and Bit[31:16] is for EMRS command cycle. You can program
this register as memory type you are using. Each 16-bit exactly map the (E)MRS register bit location. Refer to
memory data sheet.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
6-12
Specifications and information herein are subject to change without notice.
Address R/W
0x4800000C R/W
Bit Description
Bank address for EMRS
Should be '0'
DS(Driver Strength) for EMRS
Should be '0'
PASR(Partial Array Self Refresh) for EMRS
Bank address for MRS
Should be '0'
CAS Latency for MRS
00 = Reserved 01 = 1-clock
[3] DRAM Burst Type (Read Only)
Only support sequential burst type.
DRAM Burst Length (Read Only)
This value is determined internally.
S3C2451X RISC MICROPROCESSOR
Description
Mobile DRAM (E)MRS Register
10 = 2-clock 11 = 3-clock
Reset Value
0x8000_0003
Initial State
10b
0000000b
00b
00b
000b
0b
000000000b
000b
0b
011b