Samsung S3C2451X User Manual page 123

S3C2451X RISC MICROPROCESSOR
BUS TURNAROUND
You can configure the SMC for each memory bank to use external bus turnaround cycles between read and write
memory accesses. You can program the IDCY field for up to 15 bus turnaround wait states. This avoids bus
contention on the external memory data bus. Bus turnaround cycles are generated between external bus transfers
as follows:
read-to-read, to different memory banks
read-to-write to the same memory banks
read-to-write to different memory banks
Figure 5-12 shows a zero wait asynchronous read followed by two zero wait asynchronous writes with two
turnaround cycles added. The standard minimum of two AHB wait states are added to the read transfer, one is
added to the first write, as for any read-write transfer sequence, and three are added to the second write because
of insertion of the two turnaround cycles that are only generated after the first write transfer has been detected,
and the standard one wait state added when a write transfer is buffered.
Turnaround Cycles
SMCLK
ADDR
DATA(IN)
DATA(OUT)
nOE
nCS
nWE
Figure 5-12. Read, then two Writes (WSTRD=WSTWR=0), Two Turnaround Cycles (IDCY=2)
D(A)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
A
IDCY=2
STATIC MEMORY CONTROLLER
B
D(B) D(C)
C
5-11