Samsung S3C2451X User Manual page 503

S3C2451X RISC MICROPROCESSOR
HOST CONTROL REGISTER
This register contains the SD Command Argument.
Register
HOSTCTL0
HOSTCTL1
Name Bit
Reserved
CDSI [7]
GSEL
This field should be fixed to LOW
Reserved
CDTE [6]
STLVL
This field should be fixed to LOW
Extended Data Transfer Width (It is for MMC 8bit card.)
WIDE [5]
'1' = 8 bit operation
8
'0' = the bit width is designated by the bit 1 (Data Transfer Width)
DMA Select
DMAS [4:3]
One of supported DMA modes can be selected. The host driver shall check
EL
support of DMA modes by referring the Capabilities register. Use of selected DMA
is determined by DMA Enable of the Transfer Mode register.
00 = SDMA is selected
01 = Reserved
10 = 32-bit Address ADMA2 is selected
11 = 64-bit Address ADMA2 is selected (Not supported)
High Speed Enable
ENHI [2]
This bit is optional. Before setting this bit, the Host Driver shall check the High
GHSP
Speed Support in the Capabilities register. If this bit is set to 0 (default), the Host
D
Controller outputs CMD line and DAT lines at the falling edge of the SD Clock (up
to 25MHz). If this bit is set to 1, the Host Controller outputs CMD line and DAT lines
at the rising edge of the SD Clock (up to 50MHz).
'1' = High Speed mode
'0' = Normal Speed mode
Data Transfer Width
WIDE [1]
This bit selects the data width of the Host Controller. The Host Driver shall set it to
4
match the data width of the SD card.
'1' = 4-bit mode
'0' = 1-bit mode
LED Control
ONLE [0]
This bit is used to caution the user not to remove the card while the SD card is
D
being accessed. If the software is going to issue multiple SD commands, this bit
can be set during all these transactions. It is not necessary to change for each
transaction.
'1' = LED on
'0' = LED off
Note : LED port is mapped to SD0_LED pin
Note : Card Detect Pin Level does not simply reflect SDCD# pin, but chooses from SDCD, DAT[3], or
CDTestlvl depending on CDSSigSel and SDCDSel values.
Address
0X4AC00028
0X4A800028
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
R/W
R/W Present State Register (Channel 0)
R/W Present State Register (Channel 1)
Description
HSMMC CONTROLLER
Description Reset Value
0x0
0x0
Initial
Value
0
0
0
0
0
0
0
21-35