Samsung S3C2451X User Manual page 588

LCD CONTROLLER
Main LCD i80-System Interface control
Register
SYSIFCON0 0x4C800130
SYSIFCON1 0x4C800134
SYSIFCONx
Reserved
LCD_CS_SETUP
LCD_WR _SETUP
LCD_WR_ACT
LCD_WR _HOLD
Reserved
RSPOL
SUCCEUP
SYSIFEN
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
22-48
Specifications and information herein are subject to change without notice.
Address R/W
R/W i80-System Interface control for Main LDI(LCD)
R/W i80-System Interface control for Sub LDI(LCD)
Bit
[23:20] Reserved
[19:16] Numbers of clock cycles for the active period of the address
signal enable to the chip select enable.
[15:12] Numbers of clock cycles for the active period of the CS
signal enable to the write signal enable.
[11:8] Numbers of clock cycles for the active period of the chip
select enable.
[7:4] Numbers of clock cycles for the active period of the chip
select disable to the write signal disable.
[3] Reserved
[2] The polarity of the RS Signal
0: Low
* Set to 1 for normal access.
[1] 1: triggered mode(Should be 1)
[0] LCD i80-System Interface control
0: Disable
1: Enable
Description
Description
1: High
S3C2451X RISC MICROPROCESSOR
Reset Value
0x0000_0000
0x0000_0000
Initial State
0
0
0
0
0
0
0
0
0