Samsung S3C2451X User Manual page 376

USB2.0 DEVICE
USB 2.0 FUNCTION CONTROLLER SPECIAL REGISTERS
The USB 2.0 controller includes several 16-bit registers for the endpoint programming and debugging. The
registers can be grouped into two categories. Few of the indexed registers are related to endpoint 0, but most of
them are utilized for the control and status monitoring of each data endpoint, including FIFO control and packet
size configuration. The buffer register for TX/RX data buffering also belong to the indexed register/
The non-indexed registers are mainly used for the control and status checking of the system. The control and
status registers of endpoint0 belong to these non-indexed registers.
Register
IR 0x4980_0000
EIR 0x4980_0004
EIER 0x4980_0008
FAR 0x4980_000C
EDR 0x4980_0014
TR 0x4980_0018
SSR 0x4980_001C
SCR 0x4980_0020
EP0SR 0x4980_0024
EP0CR 0x4980_0028
EP0BR 0x4980_0060
EP1BR 0x4980_0064
EP2BR 0x4980_0068
EP3BR 0x4980_006C
EP4BR 0x4980_0070
EP5BR 0x4980_0074
EP6BR 0x4980_0078
EP7BR 0x4980_007C
EP8BR 0x4980_0080
FCON 0x4980_0100
FSTAT 0x4980_0104
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
17-4
Specifications and information herein are subject to change without notice.
Table 17-1. Non-Indexed Registers
Address R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Index Register
Endpoint Interrupt Register
Endpoint Interrupt Enable Register
Function Address Register
Endpoint Direction Register
Test Register
System Status Register
System Control Register
EP0 Status Register
EP0 Control Register
EP0 Buffer Register
EP1 Buffer Register
EP2 Buffer Register
EP3 Buffer Register
EP4 Buffer Register
EP5 Buffer Register
EP6 Buffer Register
EP7 Buffer Register
EP8 Buffer Register
Burst FIFO-DMA Control
Burst FIFO status
S3C2451X RISC MICROPROCESSOR
Description