Samsung S3C2451X User Manual page 61

S3C2451X RISC MICROPROCESSOR
Register Name
BLKSIZE
BLKCNT
ARGUMENT
TRNMOD
CMDREG
RSPREG0
RSPREG1
RSPREG2
RSPREG3
BDATA
PRNSTS
HOSTCTL
PWRCON
BLKGAP
WAKCON
CLKCON
TIMEOUTCON
SWRST
NORINTSTS
ERRINTSTS
NORINTSTSEN
ERRINTSTSEN
NORINTSIGEN
ERRINTSIGEN
ACMD12ERRSTS
CAPAREG
MAXCURR
FEAER
FEERR
ADMAERR
ADMASYSADDR
Address Reset Value
0x4A800004 0x00000000
0x4A800006 0x00000000
0x4A800008 0x00000000
0x4A80000C 0x00000000
0x4A80000E 0x00000000
0x4A800010 0x00000000
0x4A800014 0x00000000
0x4A800018 0x00000000
0x4A80001C 0x00000000
0x4A800020 Not fixed
0x4A800024 0x00000000
0x4A800028 0x00000000
0x4A800029 0x00000000
0x4A80002A 0x00000000
0x4A80002B 0x00000000
0x4A80002C 0x00000000
0x4A80002E 0x00000000
0x4A80002F 0x00000000
0x4A800030 0x00000000
0x4A800032 0x00000000
0x4A800034 0x00000000
0x4A800036 0x00000000
0x4A800038 0x00000000
0x4A80003A 0x00000000
0x4A80003C 0x00000000
0x4A800040 0x05E80080
0x4A800048 0x00000000
0x4A800050 0x00000000
0x4A800052 0x00000000
0x4A800054 0x00000000
0x4A800058 0x00000000
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Acc. Read/
Unit Write
HW R/W Host DMA Buffer Boundary and
Transfer Block Size Register
HW R/W Blocks Count For Current Transfer
HW R/W Command Argument Register
HW R/W Transfer Mode Setting Register
HW R/W
W ROC
W ROC
W ROC
W ROC
W ROC
W ROC
B R/W
B R/W
B R/W Block Gap Control Register
B R/W
HW R/W
B R/W
B R/W
HW ROC/ Normal Interrupt Status Register
RW1C
HW ROC/ Error Interrupt Status Register
RW1C
HW R/W Normal Interrupt Status Enable
HW R/W Error Interrupt Status Enable Register
HW R/W Normal Interrupt Signal Enable
HW R/W Error Interrupt Signal Enable Register
HW ROC Auto CMD12 Error Status Register
W HWInit
W HWInit Maximum Current Capabilities
HW WO Force Event Auto CMD12 Error
Interrupt Register Error Interrupt
HW WO Force Event Error Interrupt Register
W R/W ADMA Error Status Register
W R/W ADMA System Address Register
PRODUCT OVERVIEW
Function
Command Register
Response Register 0
Response Register 1
Response Register 2
Response Register 3
Buffer Data Register
Present State Register
Present State Register
Present State Register
Wakeup Control Register
Command Register
Timeout Control Register
Software Reset Register
Register
Register
Capabilities Register
Register
Error Interrupt
1-57