Samsung S3C2451X User Manual page 595

S3C2451X RISC MICROPROCESSOR
TIMING DIAGRAM
VSYNC
HREF
HREF (1H)
PCLK
DATA[7:0]
FieldMode = 1 (Field port connects with FIELD)
FIELD FIELD
VSYN VSYN
C C
PCLK
DATA[7:0]
Y Cb Y Cr
Figure 23-2. ITU-R BT 601 Input timing diagram
Field 1
Figure 23-3. ITU-R BT 601 interlace timing diagram
FF 00 00 XY
Video timing
reference codes
Figure 23-4. ITU-R BT 656 Input timing diagram
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1 frame
Vertical lines
Horizontal width
8-bit mode
Y Cb Y
Y Cb Cr
Pixel data
CAMERA INTERFACE
Cb Y Cr
Field 2
FF 00 00 XY
Video timing
reference codes
23-3