Samsung S3C2451X User Manual page 362

UART
UART TX/RX STATUS REGISTER
There are four UART Tx/Rx status registers including UTRSTAT0, UTRSTAT1, UTRSTAT2 and UTRSTAT3 in
the UART block.
Register
UTRSTAT0 0x50000010
UTRSTAT1 0x50004010
UTRSTAT2 0x50008010
UTRSTAT3 0x5000C010
UTRSTATn
Transmitter
empty
Transmit buffer
empty
Receive buffer
data ready
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
15-14
Specifications and information herein are subject to change without notice.
Address R/W
R UART channel 0 Tx/Rx status register
R UART channel 1 Tx/Rx status register
R UART channel 2 Tx/Rx status register
R UART channel 3 Tx/Rx status register
Bit
[2] Set to 1 automatically when the transmit buffer register has no
valid data to transmit and the transmit shift register is empty.
0 = Not empty
1 = Transmitter (transmit buffer & shifter register) empty
[1] Set to 1 automatically when transmit buffer register is empty.
0 =The buffer register is not empty
1 = Empty
(In Non-FIFO mode, Interrupt or DMA is requested.
In FIFO mode, Interrupt or DMA is requested, when Tx
FIFO Trigger Level is set to 00 (Empty))
If the UART uses the FIFO, users should check Tx FIFO Count
bits and Tx FIFO Full bit in the UFSTAT register instead of this
bit.
[0] Set to 1 automatically whenever receive buffer register contains
valid data, received over the RXDn port.
0 = Empty
1 = The buffer register has a received data
(In Non-FIFO mode, Interrupt or DMA is requested)
If the UART uses the FIFO, users should check Rx FIFO Count
bits and Rx FIFO Full bit in the UFSTAT register instead of this
bit.
S3C2451 RISC MICROPROCESSOR
Description
Description
Reset Value
0x6
0x6
0x6
0x6
Initial State
1
1
0