Samsung S3C2451X User Manual page 126

Risc microprocessor
Table of Contents

Advertisement

STATIC MEMORY CONTROLLER
SPECIAL REGISTERS
BANK IDLE CYCLE CONTROL REGISTERS 0-5
Register
SMBIDCYR0
0x4F000000
SMBIDCYR1
0x4F000020
SMBIDCYR2
0x4F000040
SMBIDCYR3
0x4F000060
SMBIDCYR4
0x4F000080
SMBIDCYR5
0x4F0000A0
[31:4]
IDCY
BANK READ WAIT STATE CONTROL REGISTERS 0-5
Register
SMBWSTRDR0
0x4F000004
SMBWSTRDR1
0x4F000024
SMBWSTRDR2
0x4F000044
SMBWSTRDR3
0x4F000064
SMBWSTRDR4
0x4F000084
SMBWSTRDR5
0x4F0000A4
[31:5]
WSTRD
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
5-14
Specifications and information herein are subject to change without notice.
Address
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Read undefined. Write as zero.
[3:0]
Idle or turnaround cycles. Default to 1111 at reset.
This field controls the number of bus turnaround cycles added
between read and write accesses to prevent bus contention on
the external memory data bus.
Turnaround time = IDCY x SMCLK period
Address
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Read undefined. Write as zero.
[4:0]
Read wait state. Defaults to 11111 at reset.
For SRAM and ROM, the wSTRD field controls the number of
wait states for read accesses, and the external wait assertion
timing for reads.
For burst ROM, the WSTRD field controls the number of wait
states for the first read access only.
Wait state time = WSTRD x SMCLK period
Description
Bank0 idle cycle control register
Bank1 idle cycle control register
Bank2 idle cycle control register
Bank3 idle cycle control register
Bank4 idle cycle control register
Bank5 idle cycle control register
Description
Description
Bank0 read wait state control register
Bank1 read wait state control register
Bank2 read wait state control register
Bank3 read wait state control register
Bank4 read wait state control register
Bank5 read wait state control register
Description
S3C2451X RISC MICROPROCESSOR
Reset Value
Initial State
Reset Value
Initial State
0xF
0xF
0xF
0xF
0xF
0xF
0x0
0xF
0x1F
0x1F
0x1F
0x1F
0x1F
0x1F
0x0
0x1F

Advertisement

Chapters

Table of Contents
loading

Table of Contents