Samsung S3C2451X User Manual page 107

S3C2451X RISC MICROPROCESSOR
3
BUS MATRIX & EBI
OVERVIEW
S3C2451 MATRIX provides the interface between dual AHB bus and Memory sub-system. It is used for achieving
high system performance by accessing various kinds of memory (SDRAM, SRAM, Flash Memory, ROM etc) from
different AHB bus (one is for system and the other is for image) at the same time. S3C2451 have two MATRIX
cores because it has two memory ports, and each MATRIX can select the priority between rotation type and fixed
type. User can select which one is excellent for improving system performance.
AHB-S
AHB-I
Figure 3-1. The configuration of MATRIX and Memory sub-system of S3C2451
Matrix
SFR
MATRIX
CORE0
MATRIX
CORE1
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Memory Controller & EBI
IROM
SSMC
NFCON
EBI
CFCON
DRAMC
BUS MATRIX & EBI
External Memory
SROM
NFLASH
CF
SDRAM
3-1