Samsung S3C2451X User Manual page 746

ELECTRICAL DATA
(VDDi= 1.3V± 0.05V (400MHz), VDDi= TBD V± 0.05V (533MHz), TA = -40 to 85°C, VDD_OP1 = 3.3V ± 0.3V)
Parameter
Crystal clock input frequency
Crystal clock input cycle time
External clock input frequency
External clock input cycle time
External clock input low level pulse width
External clock input high level pulse width
External clock to HCLK (without PLL)
HCLK (internal) to CLKOUT
HCLK (internal) to SCLK
Reset assert time after clock stabilization
PLL Lock Time
Sleep mode return oscillation setting time.
The interval before CPU runs after nRESET is
released.
NOTE: (1) If does not use MPLL, External clock input range is 10MHz ~ 133MHz but if use MPLL , External clock input
range is 10MHz ~ 30MHz
(2) tOSC2 is programmable by setting the PWRSETCNT bits in Reset Count register.
tOSC2 = (PWRSETCNT+1) * 2048
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
29-22
Specifications and information herein are subject to change without notice.
Table 29-12. Clock Timing Constants
(1)
(1)
(2)
S3C2451X RISC MICROPROCESSOR
Symbol Min
f
10
XTAL
t
33
XTALCYC
f
10
EXT
t
7.5
EXTCYC
t
3.5
EXTLOW
t
3.5
EXTHIGH
t
5
EX2HC
t 3.3
HC2CK
t
1.9
HC2SCLK
t
4
RESW
t
300
PLL
t
2
OSC2
t
5
RST2RUN
Typ Max
- 30
- 100
133
100
-
-
13
8.8
5.8
- XTIpll or
EXTCLK
-
524290 XTIpll or
EXTCLK
- XTIpll or
EXTCLK
Unit
MHz
ns
MHz
ns
ns
ns
ns
ns
ns
us