Samsung S3C2451X User Manual page 483

S3C2451X RISC MICROPROCESSOR
START
(1)
Set System Address Reg
(2)
Set Block Size Reg
(3)
Set Block Count Reg
(4)
Set Argument Reg
(5)
Set Transfer Mode Reg
(6)
Set Command Reg
(7)
Wait for Command
Complete Int
(8)
Clr Command Complete
Status
(9)
Get Response Data
Figure 21-12 Transaction Control with Data Transfer Using DAT Line Sequence (Using DMA)
(1) Set the system address for DMA in the System Address register.
(2) Set the value corresponding to the executed data byte length of one block in the Block Size register.
(3) Set the value corresponding to the executed data block count in the Block Count register(BLKCNT).
(4) Set the value corresponding to the issued command in the Argument register(ARGUMENT).
(5) Set the values for Multi / Single Block Select and Block Count Enable.
And at this time, set the value corresponding to the issued command for Data Transfer Direction, Auto CMD12
Enable and DMA Enable.
(6) Set the value corresponding to the issued command in the Command register(CMDREG).
Note: When writing to the upper byte of the Command register, the SD command is issued and DMA is started.
Command Complete Int occur
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
(10)
Wait for Transfer
Complete Int and DMA Int
(11)
Check Interrupt Status
DMA Int occur
(12)
Clr DMA Status Interrupt
(13)
Set System Address Reg
HSMMC CONTROLLER
Transfer Complete Int
occur
(14)
Clr Transfer Complete status
Clr DMA Interrupt status
END
21-15