Samsung S3C2451X User Manual page 413

S3C2451X RISC MICROPROCESSOR
FLOWCHARTS OF OPERATIONS IN EACH MODE
The following steps must be executed before any IIC Tx/Rx operations.
1. Write own slave address on IICADD register, if needed.
2. Set IICCON register.
a) Enable interrupt
b) Define SCL period
3. Set IICSTAT to enable Serial Output
START
Master Tx mode has been
configured.
Write slave address to
IICDS.
Write 0xF0 (M/T Start) to
IICSTAT.
The data of the IICDS is
transmitted.
ACK period and then
interrupt is pending.
Stop?
N
Write new data transmitted
to IICDS.
Clear pending bit to
resume.
The data of the IICDS is
shifted to SDA.
Figure 18-6. Operations for Master/Transmitter Mode
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Y
Write 0xD0 (M/T Stop) to
IICSTAT.
Clear pending bit .
Wait until the stop
condition takes effect.
END
IIC-BUS INTERFACE
18-7