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INTERRUPT CONTROLLER
INTSUBMASK
Reserved
SUBINT_DMA7
SUBINT_DMA6
SUBINT_AC97
SUBINT_WDT
SUBINT_ERR3
SUBINT_TXD3
SUBINT_RXD3
SUBINT_DMA5
SUBINT_DMA4
SUBINT_DMA3
SUBINT_DMA2
SUBINT_DMA1
SUBINT_DMA0
SUBINT_LCD4
(i80 I/F)
SUBINT_LCD3
(LCD Frame)
SUBINT_LCD2
(LCD FIFO)
Reserved
Reserved
SUBINT_CAM_P
SUBINT_CAM_C
SUBINT_ADC
SUBINT_TC
SUBINT_ERR2
SUBINT_TXD2
SUBINT_RXD2
SUBINT_ERR1
SUBINT_TXD1
SUBINT_RXD1
SUBINT_ERR0
SUBINT_TXD0
SUBINT_RXD0
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
10-24
Specifications and information herein are subject to change without notice.
Bit
Description
[31]
Not used
[30]
0 = Service available, 1 = Masked
[29]
0 = Service available, 1 = Masked
[28]
0 = Service available, 1 = Masked
[27]
0 = Service available, 1 = Masked
[26]
0 = Service available, 1 = Masked
[25]
0 = Service available, 1 = Masked
[24]
0 = Service available, 1 = Masked
[23]
0 = Service available, 1 = Masked
[22]
0 = Service available, 1 = Masked
[21]
0 = Service available, 1 = Masked
[20]
0 = Service available, 1 = Masked
[19]
0 = Service available, 1 = Masked
[18]
0 = Service available, 1 = Masked
[17]
0 = Service available, 1 = Masked
[16]
0 = Service available, 1 = Masked
[15]
0 = Service available, 1 = Masked
[14]
Not used
[13]
Reserved for future usage
[12]
0 = Service available, 1 = Masked
[11]
0 = Service available, 1 = Masked
[10]
0 = Service available, 1 = Masked
[9]
0 = Service available, 1 = Masked
[8]
0 = Service available, 1 = Masked
[7]
0 = Service available, 1 = Masked
[6]
0 = Service available, 1 = Masked
[5]
0 = Service available, 1 = Masked
[4]
0 = Service available, 1 = Masked
[3]
0 = Service available, 1 = Masked
[2]
0 = Service available, 1 = Masked
[1]
0 = Service available, 1 = Masked
[0]
0 = Service available, 1 = Masked
S3C2451X RISC MICROPROCESSOR
INTMASK
INT_DMA
INT_WDT_AC97
INT_UART3
INT_DMA
INT_LCD
Reserved
INT_CAM
INT_ADC
INT_UART2
INT_UART1
INT_UART0
Initial State
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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