Samsung S3C2451X User Manual page 76

SYSTEM CONTROLLER
ARM & BUS CLOCK DIVIDE RATIO
The MSysClk is the base clock for S3C2451 system clock, such as ARMCLK, HCLK, PCLK, DDRCLK, etc.
The table 2-5 shows the clock division ratios between ARMCLK, HLCK and PCLK. This ratio is determined by
ARMDIV, PREDIV, HCLKDIV and PCLKDIV bits of CLKDIV0 control register.
ARMCLK has to faster or equal with HCLK and synchronous. The table 2-5 shows that DDRCLK, PCLK, ARMCLK
divide ratio with regard HCLK ratio.
The fraction in the cell is ratio to MSysClk and the value in the round bracket means maximum frequency value.
MSysClk
(800MHz) (133MHz)
1/1
1/2
1/3
1/4
1/6
1/8
1/12
1/16
Preliminary product information describe products that are in development,
2-10
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Table 2-5. Clock division ratio of MPLL region
HCLK DDRCLK
(266MHz)
1/1
1/1
1/1
1/2
1/3
1/4
1/6
1/8
PCLK, SSMC
(133MHz)
1/1 or 1/2 1/1
1/2 or 1/4 1/1 or 1/2
1/3 or 1/6 1/1 or 1/3
1/4 or 1/8 1/1 or 1/2 or 1/4
1/6 or 1/12 1/1 or 1/2 or 1/3 or 1/6
1/8 or 1/16 1/1 or 1/2 or 1/4 or 1/8
1/12 or 1/24 1/1 or 1/2 or 1/3 or 1/4 or 1/6
1/16 or 1/32 1/1 or 1/2 or 1/4 or 1/8
S3C2451X RISC MICROPROCESSOR
ARMCLK (533MHz)