Samsung S3C2451X User Manual page 104

SYSTEM CONTROLLER
USB PHY POWER CONTROL REGISTER (PHYPWR)
Register
PHYPWR 0x4C00_0084
PHYCTRL
COMMON_ON_N
RESERVED
ANALOG_
POWERDOWN
PLL_REF_CLK
XO_ON
PLL_
POWERDOWN
FORCE_
SUSPEND
Preliminary product information describe products that are in development,
2-38
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Address R/W
R/W
Bit
[31] Force XO(Crystal Oscillator), Bias, Bandgap, and PLL to
Remain Powered During a Suspend
This signal controls the power-down signals of sub-blocks in
the Common block when the USB 2.0 PHY is suspended.
• 0: The 48 MHz clock on clk48m_ohci is available at all times,
except in Suspend mode.
• 1: The 48 MHz clock on clk48m_ohci is available at all times,
even in Suspend mode.
This signal is a strapping option that must be tied to a valid,
static value at all times. Because the signal is a strapping
option, this pin is non-critical for STA, and any other timings or
loading limits for the pin are specified in the .lib timing model
included in the product deliverables.
NOTE: If common_on_n is set low, clk_ref_ohci and
clk12m_ohci are also available, even in Suspend mode. The
common_on_n signal overrides xo_on_n.
[30:6] -
[5:4] Analog block power down in PHY2.0
01 = Analog block power down
others = Analog block power up(Normal Operation)
[3] Switch reference clock used in Internal PLL of USB block
0 = External X-tal clock source
1 = Internal System PLL clock source (USBHOSTCLK should
be 48Mhz and The clk_sel[1:0] bus must be set to 2'b00)
[2] Force XO Block on During Suspend
1 = XO block is powered up
0 = XO block is powered down when all ports are suspended
[1] PLL power down in PHY2.0
0 = PLL power up
1 = PLL power down
[0] Apply Suspend signal for power save
0 = disable (Normal Operation)
1 = enable
Description
USB2.0 PHY Power Control Register
Description
S3C2451X RISC MICROPROCESSOR
Reset Value
0x0000_0000
Initial State
0
0
2'b00
0
0
0
0