Samsung S3C2451X User Manual page 419

S3C2451X RISC MICROPROCESSOR
MULTI-MASTER IIC-BUS ADDRESS (IICADD) REGISTER
Register
IICADD0 0x54000008
IICADD1 0x54000108
IICADD0
Bit
IICADD1
Slave address [7:0]
MULTI-MASTER IIC-BUS TRANSMIT/RECEIVE DATA SHIFT (IICDS) REGISTER
Register
IICDS0 0x5400000C
IICDS1 0x5400010C
IICDS0
Bit
IICDS1
Data shift [7:0]
Address R/W
R/W IIC0-Bus address register
R/W IIC1-Bus address register
7-bit slave address, latched from the IIC-bus.
When serial output enable = 0 in the IICSTAT, IICADD is write-
enabled. The IICADD value can be read any time, regardless of the
current serial output enable bit (IICSTAT) setting.
Slave address : [7:1]
Not mapped : [0]
Address R/W
R/W IIC0-Bus transmit/receive data shift register
R/W IIC1-Bus transmit/receive data shift register
8-bit data shift register for IIC-bus Tx/Rx operation.
When serial output enable = 1 in the IICSTAT, IICDS is write-
enabled. The IICDS value can be read any time, regardless of the
current serial output enable bit (IICSTAT) setting.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
Description
Description
IIC-BUS INTERFACE
Reset Value
0xXX
0xXX
Initial State
XXXXXXXX
Reset Value
0xXX
0xXX
Initial State
XXXXXXXX
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