Samsung S3C2451X User Manual page 522

HSMMC CONTROLLER
ERROR INTERRUPT SIGNAL ENABLE REGISTER
This register is used to select which interrupt status is notified to the Host System as the interrupt. These
status bits all share the same 1 bit interrupt line. Setting any of these bits to 1 enables interrupt generation.
Register
ERRINTSIGEN0
ERRINTSIGEN1
Name Bit
[15:10]
ENSIGADM
[9]
AERR
ENSIGACM
[8]
DERR
ENSIGCUR
[7]
ERR
ENSIGDEN
[6]
DERR
ENSIGDAT
[5]
CRCERR
ENSIGDAT
[4]
TOUTERR
ENSIGCMD
[3]
IDXERR
ENSIGCMD
[2]
EBITERR
ENSIGCMD
[1]
CRCERR
ENSIGCMD
[0]
TOUTERR
Detailed documents are to be copied from SD Host Standard Spec.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-54
Specifications and information herein are subject to change without notice.
Address
0X4AC0003A
0X4A80003A
Reserved
ADMA Error Signal Enable
'1' = Enabled
'0' = Masked
Auto CMD12 Error Signal Enable
'1' = Enabled
'0' = Masked
Current Limit Error Signal Enable
This function is not implemented in this version.
'1' = Enabled
'0' = Masked
Data End Bit Error Signal Enable
'1' = Enabled
'0' = Masked
Data CRC Error Signal Enable
'1' = Enabled
'0' = Masked
Data Timeout Error Signal Enable
'1' = Enabled
'0' = Masked
Command Index Error Signal Enable
'1' = Enabled
'0' = Masked
Command End Bit Error Signal Enable
'1' = Enabled
'0' = Masked
Command CRC Error Signal Enable
'1' = Enabled
'0' = Masked
Command Timeout Error Signal Enable
'1' = Enabled
'0' = Masked
R/W Description
R/W Error Interrupt Signal Enable Register
(Channel 0)
R/W Error Interrupt Signal Enable Register
(Channel 1)
Description
S3C2451X RISC MICROPROCESSOR
Reset Value
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0x0
0x0