Samsung S3C2451X User Manual page 514

HSMMC CONTROLLER
STATRANC [1]
MPLT
STACMDC [0]
MPLT
Note : Host Driver may check if interrupt is actually cleared by polling or monitoring the INTREQ port. If HCLK is
much faster than SDCLK, it takes long time to be cleared for the bits actually.
Note : Card Interrupt status bit keeps previous value until next card interrupt period (level interrupt) and can be
cleared when write to 1 (RW1C).
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-46
Specifications and information herein are subject to change without notice.
This bit is set at the falling edge of Write Transfer Active Status (After getting
CRC status at SD Bus timing).
'1' = Transaction stopped at block gap
'0' = No Block Gap Event
Transfer Complete
This bit is set when a read / write transfer is completed.
(1) In the case of a Read Transaction
This bit is set at the falling edge of Read Transfer Active Status. There are
two cases in which this interrupt is generated. The first is when a data transfer
is completed as specified by data length (After the last data has been read to
the Host System). The second is when data has stopped at the block gap and
completed the data transfer by setting the Stop At Block Gap Request in the
Block Gap Control register (After valid data has been read to the Host
System).
(2) In the case of a Write Transaction
This bit is set at the falling edge of the DAT Line Active Status. There are two
cases in which this interrupt is generated. The first is when the last data is
written to the SD card as specified by data length and the busy signal
released. The second is when data transfers are stopped at the block gap by
setting Stop At Block Gap Request in the Block Gap Control register and
data transfers completed. (After valid data is written to the SD card and the
busy signal released). (RW1C)
The table below shows that Transfer Complete has higher priority than
Data Timeout Error. If both bits are set to 1, the data transfer can be
considered complete.
Relation between Transfer Complete and Data
Transfer Data Timeout
Complete Error
0 0
0 1
1 Don't care
'1' = Data Transfer Complete
'0' = No transfer complete
Command Complete
This bit is set when get the end bit of the command response. (Except Auto
CMD12) Refer to Command Inhibit (CMD) in the Present State register.
The table below shows that Command Timeout Error has higher priority
than Command Complete. If both bits are set to 1, it can be considered that
the response was not received correctly.
Command Command
Complete Timeout Error
0 0
Don't care 1
1 0
'1' = Command Complete
'0' = No command complete
S3C2451X RISC MICROPROCESSOR
Meaning of the status
Interrupted by another factor
Timeout occur during transfer
Data transfer complete
Meaning of the status
Interrupted by another factor
Response not received within
64 SDCLK cycles.
Response received
0
0