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S3C2451X RISC MICROPROCESSOR
MSDMA CONTROL REGISTER
Register
CIMSCTRL
0x4D80_00DC
CIMSCTRL
Reserved
[31:7]
EOF_MS
Interleave_MS
(v)
Order422_MS
(v)
SEL_DMA_CA
M (v)
SRC420_MS (v)
ENVID_MS (v)
NOTE: ENVID_MS SFR must be set at last. Starting order for using MSDMA input path.
SEL_DMA_CAM (others SFR setting)
Address
R/W
RW
Bit
[6]
MSDMA read the saved memory data.
When this operation done, EOF will be generated. (read
only)
[5]
0 : Non-Interleaved format (Each component of Y, Cb and
Cr is access by the word).
1 : Interleaved format (All components of Y, Cb and Cr are
mixed inside single word).
[4:3]
When source MSDMA image is interleaved YCbCr 4:2:2,
Interleaved YCbCr 4:2:2 input memory storing style.
[4:3]
LSB
00
01
10
11
[2]
Preview path data selection. codec path don't care.
0 : External camera input path
1 : Memory data input path (MSDMA)
[1]
Source image format for MSDMA
0 : YCbCr 4:2:2 (interleaved)
1 : YCbCr 4:2:0 (Non-interleaved)
[0]
MSDMA operation start. Hardware doesn't clear
automatically
(When triggered Low to High by software setting)
1) SEL_DMA_CAM = '0' , ENVID_MS don't care (using
external camera signal for preview path)
2) SEL_DMA_CAM = '1', ENVID_MS is set (0 1) then
MSDMA operation start for preview. (external camera
signal is valid for only codec_path)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
MSDMA control register
Description
MSB
Y
Cb
Y
Cr
0
0
1
0
Y
Cr
Y
Cb
0
0
1
0
Cb
Y
Cr
Y
0
0
0
1
Cr
Y
Cb
Y
0
0
0
1
Image Capture Enable SFR setting
CAMERA INTERFACE
Reset Value
0000_0000
Initial
State
0
0
0
0
0
0
0
ENVID_MS SFR setting.
Change
State
X
X
X
X
X
X
X
23-47
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