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CF CONTROLLER
ATA_SWRST REGISTER
Register
ATA_SWRST
0x4B80190C
ATA_SWRST
Reserved
ata_swrstn
ATA_IRQ REGISTER
Register
ATA_IRQ
0x4B801910
ATA_IRQ
Bits
Reserved
[31:5]
sbuf_empty_int
tbuf_full_int
atadev_irq_int
reserved
xfr_done_int
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
8-18
Specifications and information herein are subject to change without notice.
Address
R/W
R/W
ATA S/W RESET register
Bits
[31:1]
Reserved bits
[0]
Software reset for the ATA host
0: No reset
1: Software reset for all ATA host module.
After software reset, to continue transfer, user must
configure all registers of host controller and device
registers.
Address
R/W
R/W
Reserved bits
[4]
When source buffer is empty.
CPU can clear this interrupt by writing "1".
[3]
When track buffer is half full.
CPU can clear this interrupt by writing "1".
[2]
When ATA device generates interrupt.
CPU can clear this interrupt by writing "1".
[1]
reserved
[0]
When all data transfers are finished.
CPU can clear this interrupt by writing "1".
Description
Description
Description
ATA IRQ register
Description
S3C2451X RISC MICROPROCESSOR
Reset Value
0x0000_0000
R/W
Reset Value
R
R/W
Reset Value
0x0000_0000
R/W
Reset Value
R
R/W
R/W
R/W
R/W
R/W
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
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