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I/O PORTS
EINTMASK (External Interrupt Mask Register)
Register
EINTMASK
EINTMASK
Reserved
EINT23
EINT22
EINT21
EINT20
EINT19
EINT18
EINT17
EINT16
EINT15
EINT14
EINT13
EINT12
EINT11
EINT10
EINT9
EINT8
EINT7
EINT6
EINT5
EINT4
Reserved
11-42
Address
R/W
0x560000a4
R/W
Bit
[31:24]
Reserved
[23]
0 = enable interrupt
[22]
0 = enable interrupt
[21]
0 = enable interrupt
[20]
0 = enable interrupt
[19]
0 = enable interrupt
[18]
0 = enable interrupt
[17]
0 = enable interrupt
[16]
0 = enable interrupt
[15]
0 = enable interrupt
[14]
0 = enable interrupt
[13]
0 = enable interrupt
[12]
0 = enable interrupt
[11]
0 = enable interrupt
[10]
0 = enable interrupt
[9]
0 = enable interrupt
[8]
0 = enable interrupt
[7]
0 = enable interrupt
[6]
0 = enable interrupt
[5]
0 = enable interrupt
[4]
0 = enable interrupt
[3:0]
Reserved
Description
External interrupt mask register
Description
1= masked
1= masked
1= masked
1= masked
1= masked
1= masked
1= masked
1= masked
1= masked
1= masked
1= masked
1= masked
1= masked
1= masked
1= masked
1= masked
1= masked
1= masked
1= masked
1= masked
S3C2451X RISC MICROPROCESSOR
Reset Value
0x00fffff0
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