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S3C2451X RISC MICROPROCESSOR
IIS FIFO CONTROL REGISTER (IISFIC)
Register
IISFIC
IISFIC
FTX2CNT
FTX1CNT
TFLUSH
FTX0CNT
RFLUSH
FRXCNT
NOTES:
Tx FIFOs, Rx FIFO has 32-bit width and 16 depth structure, so FIFO data count value ranges from 0 to 16.
IIS PRESCALER CONTROL REGISTER (IISPSR)
Register
IISPSR
IISPSR
PSRAEN
PSVALA
Address
0x55000008
Bit
R/W
[31:29]
R/W
Reserved. Program to zero.
[28:24]
R
TX FIFO2 data count. (0 ~ 16)
[23:21]
R/W
Reserved. Program to zero.
[20:16]
R
TX FIFO1 data count. (0~16)
[15]
R/W
TX FIFO flush command.
0: No flush, 1: Flush
[14:13]
R/W
Reserved. Program to zero.
[12:8]
R
TX FIFO0 data count. (0~16)
[7]
R/W
RX FIFO flush command.
0: No flush, 1: Flush
[6:5]
R/W
Reserved. Program to zero.
[4:0]
R
RX FIFO data count. (0~16)
Address
0x5500000C
IIS interface clock divider control register
Bit
R/W
[31:16]
R/W
Reserved. Program to zero.
[15]
R/W
Pre-scaler (Clock divider) active.
1: Active (divide I2SAudioCLK with Pre-scaler division value)
0: Inactive (bypass I2SAudioCLK)
(Refer to Figure 26-2)
[14]
R/W
Reserved. Program to zero.
[13:8]
R/W
Pre-scaler (Clock divider) division value.
N: Division factor is N+1 (1~1/64)
[7:0]
R/W
Reserved. Program to zero.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
IIS interface FIFO control register
Description
Description
Description
IIS MULTI AUDIO INTERFACE
Reset Value
0x0000_0000
Reset Value
0x0000_0000
26-19
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