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S3C2451X RISC MICROPROCESSOR
INTERRUPT CONTROLLER OPERATION
F-bit and I-bit of Program Status Register (PSR)
If the F-bit of PSR in ARM926EJ CPU is set to 1, the CPU does not accept the Fast Interrupt Request (FIQ) from
the interrupt controller. Likewise, If I-bit of the PSR is set to 1, the CPU does not accept the Interrupt Request
(IRQ) from the interrupt controller. So, the interrupt controller can receive interrupts by clearing F-bit or I-bit of the
PSR to 0 and setting the corresponding bit of INTMSK to 0.
Interrupt Mode
The ARM926EJ has two types of Interrupt mode: FIQ or IRQ. All the interrupt sources determine which mode is
used at interrupt request.
Interrupt Pending Register
The S3C2451X has two interrupt pending resisters: source pending register (SRCPND) and interrupt pending
register (INTPND). These pending registers indicate whether or not an interrupt request is pending. When the
interrupt sources request interrupt service, the corresponding bits of SRCPND register are set to 1, and at the
same time, only one bit of the INTPND register is set to 1 automatically after arbitration procedure. If interrupts are
masked, the corresponding bits of the SRCPND register are set to 1. This does not cause the bit of INTPND
register changed. When a pending bit of the INTPND register is set, the interrupt service routine starts whenever
the I-flag or F-flag is cleared to 0. The SRCPND and INTPND registers can be read and written, so the service
routine must clear the pending condition by writing a 1 to the corresponding bit in the SRCPND register first and
then clear the pending condition in the INTPND registers by using the same method.
Interrupt Mask Register
This register indicates that an interrupt has been disabled if the corresponding mask bit is set to 1. If an interrupt
mask bit of INTMSK is 0, the interrupt will be serviced normally. If the corresponding mask bit is 1 and the
interrupt is generated, the source pending bit will be set.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
INTERRUPT CONTROLLER
10-3
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