Samsung S3C2451X User Manual page 87

S3C2451X RISC MICROPROCESSOR
INDIVIDUAL REGISTER DESCRIPTIONS
CLOCK SOURCE CONTROL REGISTERS (LOCKCON0, LOCKCON1, OSCSET, MPLLCON, AND EPLLCON)
The six registers control two internal PLLs and an external oscillator. The output frequency of the PLL is
determined by the divider values of MPLLCON and EPLLCON. The stabilization time for PLLs and the oscillator is
controlled by LOCKCON0/1 and OSCSET, respectively.
Register
LOCKCON0 0x4C00_0000
LOCKCON1 0x4C00_0004
OSCSET 0x4C00_0008
MPLLCON 0x4C00_0010
EPLLCON 0x4C00_0018
EPLLCON_K 0x4C00_001C
Conventional PLL requires stabilization duration after the PLL is ON. The duration can be varied according to the
device variation. Thus, software must adjust these fields with appropriate values in the LOCKCON0/1 register
whose values mean the number of the external reference clock.
LOCKCON0
RESERVED
M_LTIME
LOCKCON1
RESERVED
E_LTIME
In general, an oscillator requires stabilization time. This register specifies the duration based on the reference
clock.
OSCSET
RESERVED
XTALWAIT
Address R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
[31:16] RESERVED
MPLL lock time count value for ARMCLK, HCLK, and PCLK
[15:0]
Typically, M_LTIME must be longer than 300 usec.
Bit
[31:16] RESERVED
EPLL lock time count value for UARTCLK, SPICLK and etc.
[15:0]
Typically, E_LTIME must be longer than 300 usec.
Bit
[31:0] RESERVED
Crystal oscillator settle-down wait time, this value is valid
[15:0]
when s3c2451 is wakeup by stop mode
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
MPLL lock time count register
EPLL lock time count register
Oscillator stabilization control register
MPLL configuration register
EPLL configuration register
EPLL configuration register for K value
Description
Description
Description
SYSTEM CONTROLLER
Reset Value
0x0000_FFFF
0x0000_FFFF
0x0000_8000
0x0185_40C0
0x0120_0102
0x0000_0000
Initial Value
0x0000
0xFFFF
Initial Value
0x0000
0xFFFF
Initial Value
0x0000
0x8000
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